Complementary metal oxide semiconductor (CMOS) circuits may contain thousands or millions of transistors and other circuit elements. The design of such circuits is extremely complicated and usually employs simulators, such as SPICE, to predict circuit operation. In addition to predicting the operation of the circuit when it is new, it is frequently important to simulate the operation of the circuit as it ages from processes such as hot carrier effects.
FIG. 1 is a schematic of a field effect transistor, the example here being a P-channel MOSFET formed on a silicon substrate, although much of the following discussion applies NMOS transistors and other insulated gate devices. This device may also have a lightly doped drain (LDD) region that is not shown in FIG. 1. Some of the particulars for the NMOS case will be discussed later. The transistor 10 has a bulk N-type region 5, source region 11 and drain region 12 defined at and below the substrate surface, and a lightly doped N-type channel region 15 having a manufactured length LM in the region between the source 11 and the drain 12. Over the channel region is an oxide or other insulating layer 14 that supports the gate 13. (Here the gate is shown doped as N+, although in a PMOS this may alternately be P+.) When the transistor is turned on, current flows through the channel region below the oxide/silicon interface.
With operation over time, the PMOS transistor 10 will suffer degradation due to device aging. An important mechanism in the aging of insulated gate devices is the “hot carrier” effect. When the transistor is turned on, a current Ids of energized charge carriers flows through the channel 15 from the source 11 to the drain 12. Impact of these charge carriers near the channel/drain juncture generates electron-hole pairs. Some of the resultant electrons have sufficient energy to pass through the insulating layer 14 by tunneling or other leakage mechanisms and are then collected at the gate 13, resulting in a gate current IG. The rest of the electrons result in a substrate current Isub contribution, with generated holes adding to the drain current Ids. Some of the impact induced electrons become trapped inside of the insulating layer 14 or become trapped at the interface of the channel 15 and the insulating layer 14. This attracts holes to the channel side of the channel/insulator interface, which cause the effective boundary of the P+ drain region 12 to shift closer to the source region. This is shown in FIG. 2, where drain is extended by the region 12′, shortening the effective channel length to L′<LM. Additionally, the oxide/silicon interface above channel region is damaged by the more energetic holes and electrons.
These effects degrade the transistor's operation in several ways. As these charges accumulate, the voltage needed at the gate to turn on the transistor, the device's threshold voltage Vth, changes, resulting in positive shift, ΔVth>0. This makes the PMOS threshold voltage less negative and reduces the Vth value at which the onset of leakage current is seen. When a sufficient number of trapped electrons are distributed over the manufactured length LM of the channel 15, a relatively large leakage current will flow through the transistor even when the gate voltage VG is set to an “off” level.
The damage to the interface results in a lower mobility, μ, as the carriers flow form source 11 to drain 12. The lower mobility results in more resistance and lowers Ids, where as the electrons trapped in the dielectric tend to raise the PMOS's Ids curve. The strength of these effects depend differently on bias conditions, but traditionally the change due to lower mobility has been smaller; however, as device sizes have decreased, this interface damage becomes more significant and, depending upon bias conditions, often becomes the larger effect below a quarter micron or so.
These problems are aggravated as device sizes decrease into the submicron region. One reason is that an amount of incursion of the region 12′ that produces a relatively small relative change for a channel length of, say, LM≈1.5 μm becomes a much larger relative change at LM≈0.25 μm. For example, if 12′ extends an absolute distance of 0.05 μm, this produces a change of
            (                        L          ′                -                  L          M                    )              L      M        =            -      20        ⁢                  ⁢    %  for the shorter channel length, but of only −3% at the longer length. Another reason is that as the electric field in the channel is given by
      E    =                  V        ds            L        ,the resultant field strength, and consequently the number of electron/hole pairs produced, increases greatly in a submicron device even at low power operation. For example, in a LM=0.25 μm MOSFET operating at 2.5 volts results in fields of ≈107 V/m. As L′ departs further and further from LM, the field strengths increase resulting in an even greater electron/hole pair production rate.
In the case of an NMOS transistor, the results of hot-carriers differ in several respects. Electrons will again be trapped in the dielectric and as the number of electrons in the oxide increases, a positive shift in voltage will again be needed at the gate to turn on the transistor results, ΔVth>0. As Vth is positive now, the threshold voltage becomes larger in magnitude and the Ids curve is lowered as the gate voltage must additionally overcome the negative charge embedded in the dielectric to cause the channel inversion.
The damage to the interface again lowers the mobility, μ, as the electrons flow form source 11 to drain 12, resulting in more resistance and lowering Ids. Thus in this case, both effects move the Ids curve in the same direction. Also as with the PMOS, the strength of these effects depends differently on bias conditions, with the change due to lower mobility traditionally smaller but becoming increasingly important as device size shrink. Unlike the PMOS, though, the effective channel length does not decrease.
These hot electron effects build up over time causing the device to degrade as it ages. To determine the aging of a circuit as a whole, the degradation of the various devices within the circuit must be considered. As an example, consider the simple circuit shown in the schematic of FIG. 3, consisting of three inverters manufactured to be identical.
FIG. 3 shows three inverters, 20a, 20b, and 20c, connected in parallel with a capacitive load C 25a, 25b, and 25c connected to the output of each. Each of these inverters consists of a circuit like that of FIG. 4, with a PMOS transistor Pa 21 and an NMOS transistor Na 22 connected as shown. To simulate the fresh circuit, a circuit simulation, such as of the SPICE or timing simulation type, can be performed using the same model card for each of PMOS transistors 21 and the same model card for each of the NMOS transistors.
To simulate the aged circuit, a model card representing the aged behavior of each of the elements needs to be used. To determine how the aged device will operate, the device is stressed to obtain the aging model information from the electrical test data. From this, the aged model card for the device can be extracted. However, the same aged model card can no longer be used for all of the similar devices. To see why, consider FIG. 3 again.
The amount of degradation in the PMOS 21 and the NMOS 22 of inverter 20a depends on the input signal supplied at node X, while the degradation in inverters 20b and 20c will instead depend on the input at nodes Y and Z, respectively. The waveforms at these nodes will differ from each other as the input waveform will change in both shape and magnitude as it propagates through the circuit. Thus, if the operation of a circuit after, say, 5 years, of use is simulated, the relative amount of degradation in each of the inverters will differ and, consequently, a different aged model card will be needed for each of the transistors. For even the simple circuit of FIGS. 3 and 4, this results in a three-fold increase in the required number of model cards for the aged circuit simulation compared with the fresh circuit. As a real circuit will often contain thousands or even millions of elements, the simulation of the aging of such circuits is a extremely complicated process for which a large number of improvements are desirable.